Jena/Nuremberg announces the introduction of new features for parallel Multi-Channel Bit Error Rate Tests (BERT) for its IP-based ChipVORX® technology.

The highly automated solution enables FPGA Embedded Instruments utilization in the form of special softcores for the test and design validation of multi-channel high-speed I/O and high-performance serial bus systems as e.g. PCI Express x2/x4/x8/x16.

Users can now evaluate the transmission channel quality via parallel measurement of the bit error rate on all channels at the same time. A graphical evaluation via eye diagram is possible to support design validation.

ChipVORX® takes over the complete process flow starting with Target FPGA programming, IP to pin configuration, instrument control as well as data processing and the final IP unloading. In the debug mode, the BERT parameters can be changed interactively for immediate effect without design synthesis. Integrated in the software SYSTEM CASCON™, an Automatic Application Program Generator (AAPG) for automatic test procedure generation is available. That makes the utilization of the new BERT solution highly efficient and user-friendly.

"With these new ChipVORX models for Bit Error Rate Test we are now able to cover even most complex high-speed designs with serial multi-lane bus systems of highest band width", says Bettina Richter, Marketing Manager at GOEPEL electronic“.

"By the parallel instrumentation it is not only possible to recognize interactions between channels during design validation, but also to reduce test time to a minimum. Simultaneously, we push the use of FPGA Embedded Instruments as a pathbreaking solution for quality insurance of access critical designs".

Über Bit Error Rate Test (BERT):
So called Bit Error Rates (BER) are measured to evaluate the channel quality in digital transmission systems. BER is the relation between faulty transported bits and the total number of transported bits in a certain time interval. The equipment consists basically of the pattern generator, a transceiver with error detector and a clock generator, synchronising both. The bit patterns, created by the pattern generator, are in particular important for the quality of the Bit Error Rate Test, as they have critical influence on the fault stimulation during the transmission (stress pattern). The new solution uses respective instrumentations in parallel on all transmission channels.

About Chip Embedded Instruments:
Chip embedded Instruments are permanently integrated or temporarily implemented test and measurement functions (T&M) in an integrated circuit. Virtually, they are the counterpart to external T&M instruments as they don’t require invasive contacting by means of probes or nails. Hence, the problem of signal distortion in high-speed designs by parasitic contacting effects is omitted. Chip embedded Instruments are part of the so called Embedded System Access (ESA) technologies, where also methods like Boundary Scan, Processor Emulation Test, In-System Programming or Core Assisted Programming belong to. ESA technologies are currently the most modern strategy for validation, test and debug as well as programming of complex boards and systems. They can be utilised throughout the entire product life cycle, enabling improved test coverage at reduced costs.

About ChipVORX®:
ChipVORX® is an IP-based technology for implementation, access and control of Chip embedded Instruments via IEEE Std. 1149.x/JTAG. It also supports FPGA embedded instruments in the form of softcores. The ChipVORX library currently contains more than 300 different test and measurement instruments for all leading FPGA platforms. Some of these instruments are frequency meters and high-speed Flash programmers as well as IP for at-speed access test of dynamic RAM devices. The use of ChipVORX® requires neither expert background knowledge by the user nor special FPGA tools or continous IP adaptations.

About the development, funding and availability:
The BERT instruments development as prototypes and their integration into respective system software is the result of a strategic cooperation between GOEPEL electronic and Testonica Lab. The ChipVORX® IP models for BERT will be supported in SYSTEM CASCON™ starting from version 4.6.3 , and are activated per license manager just like the system software. SYSTEM CASCON™ is GOEPEL electronic’s professional JTAG/Boundary Scan development environment with currently more than 45 fully integrated ISP, test and debug tools. In terms of hardware, ChipVORX is completely supported in the platform SCANFLEX®.

The project upon which this publication is based was funded by the Federal Minister of Education and Research within the frame of the Eurostars funding programme (E! 5568 COMBOARD).